The present invention relates in general to integrated circuit packaging, and more particularly to an improved process for fabricating a leadless plastic chip carrier which includes a post mold etch back step and a unique die attach pad design.
According to well known prior art IC (integrated circuit) packaging methodologies, semiconductor dice are singulated and mounted using epoxy or other conventional means onto respective die pads (attach paddles) of a leadframe strip. Traditional QFP (Quad Flat Pack) packages incorporate inner leads which function as lands for wire bonding the semiconductor die bond pads. These inner leads typically require mold locking features to ensure proper positioning of the leadframe strip during subsequent molding to encapsulate the package. The inner leads terminate in outer leads that are bent down to contact a mother board, thereby limiting the packaging density of such prior art devices.
In order to overcome these and other disadvantages of the prior art, the Applicants previously developed a Leadless Plastic Chip Carrier (LPCC). According to Applicants"" LPCC methodology, a leadframe strip is provided for supporting up to several hundred devices. Singulated IC dice are placed on the strip die attach pads using conventional die mount and epoxy techniques. After curing of the epoxy, the dice are gold wire bonded to peripheral internal leads. The leadframe strip is then molded in plastic or resin using a modified mold wherein the bottom cavity is a flat plate. In the resulting molded package, the die pad and leadframe inner leads are exposed. By exposing the bottom of the die attach pad, mold delamination at the bottom of the die paddle is eliminated, thereby increasing the moisture sensitivity performance. Also, thermal performance of the IC package is improved by providing a direct thermal path from the exposed die attach pad to the motherboard. By exposing the leadframe inner leads, the requirement for mold locking features is eliminated and no external lead standoff is necessary, thereby increasing device density and reducing package thickness over prior art methodologies. The exposed inner leadframe leads function as solder pads for motherboard assembly such that less gold wire bonding is required as compared to prior art methodologies, thereby improving electrical performance in terms of board level parasitics and enhancing package design flexibility over prior art packages (i.e. custom trim tools and form tools are not required). These and several other advantages of Applicants"" own prior art LPCC process are discussed in Applicants"" co-pending patent application Ser. No. 09/095,803, the contents of which are incorporated herein by reference.
Applicants"" LPCC production methodology utilizes saw singulation to isolate the perimeter I/O row as well as multi-row partial lead isolation. Specifically, the leadframe strip is mounted to a wafer saw ring using adhesive tape and saw-singulated using a conventional wafer saw. The singulation is guided by a pattern of fiducial marks on the bottom side of the leadframe strip. Also, special mold processing techniques are used to prevent the mold flow from bleeding onto the functional pad area and inhibiting electrical contact. Specifically, the exposed die pad surface is required to be deflashed after molding to remove any molding compound residue and thereby allow the exposed leads and die attach pad to serve as solder pads for attachment to the motherboard.
According to Applicants"" co-pending U.S. patent application Ser. No. 09/288,352, the contents of which are incorporated herein by reference, an etch back process is provided for the improved manufacture of the LPCC IC package. The leadframe strip is first subjected to a partial etch on one or both of the top and bottom surfaces in order to create a pattern of contact leads (pads) and a die attach pad (paddle). After wire bonding the contacts to a singulated semiconductor die, followed by overmolding and curing of the mold, the leadframe strip is exposed to a second full etch immersion for exposing the contact pads in an array pattern (i.e. multi-row) or perimeter pattern (i.e. single row), as well as the die attach pad. In the case of a package with multi-row I/O leads, this etch back step eliminates the requirement for two additional saw singulation operations (i.e. to sever the inner leads from the outer leads), and in both the single-row and multi-row configurations, the etch back step eliminates post mold processing steps (e.g. mold deflashing) and ensures superior device yield over the processing technique set forth in Applicants"" prior application Ser. No. 09/095,803. Additionally, using this technique allows for higher I/O pad density and also allows for pad standoff from the package bottom which reduces stress in the solder joint during PCB temp cycling. Further, the technique allows for the use of a pre-singulation strip testing technique given that the electrical I/O pads are now isolated from each other and testing in strip can take place. This feature greatly increased the handling and throughput of the test operation.
In Applicant""s co-pending U.S. application for a Leadless Plastic Chip Carrier With Etch Back Pad Singulation, filed concurrently herewith, the contents of which are incorporated herein by reference, the etch-back LPCC process of Applicants"" co-pending U.S. patent application Ser. No. 09/288,352 is modified to provide additional design features.
The leadframe strip is selectively covered with a thin layer photo-resist mask in predetermined areas. Following the application of the mask, an etch-barrier is deposited as the first layer of the contact pads and die attach pad, followed by several layers of metals which can include for example, Ni, Cu, Ni, Au, and Ag. This method of formation of the contact pads allows plating of the pads in a columnar shape and into a xe2x80x9cmushroom capxe2x80x9d or rivet-shape as it flows over the photoresist mask. The shaped contact pads are thereby locked in the mold body, providing superior board mount reliability. Similarly, the die attach pad can be formed in an interlocking shape for improved alignment with the die. The photo-resist mask is then rinsed away and the semiconductor die is mounted to the die attach pad. This is followed by gold wire bonding between the semiconductor die and the peripheral contact pads and then molding as described in Applicant""s application Ser. No. 09/095,803. The leadframe is then subjected to full immersion in an alkaline etchant that exposes a lower surface of an array of the contact pads, a power ring and the die attach pad, followed by singulation of the individual unit from the full leadframe array strip.
During mounting of the integrated circuit package to a printed circuit board, solder alloy on the exposed contact pads and die attach pad tend to ball up due to surface tension that can cause the integrated circuit package to lift away from the circuit board, from the center. In the case where the die attach pad is much larger than the contact pads, solder fillet of the contact pad can be weakened or broken.
According to an aspect of the present invention, a new leadless plastic chip carrier is provided. The leadless plastic chip carrier has a plurality of die attach pads on which a singulated semi-conductor die is mounted. At least one row of contact pads circumscribes the plurality of die attach pads and a power/ground ring is intermediate the contact pads and the die attach pads. Wire bonds connect the semiconductor die, the contact pads and the power/ground ring. An overmold covers the semiconductor die, the attach pads, the power/ground ring and the contact pads such that each of the die attach pads and the contact pads has one exposed surface. According to a further aspect of the invention, each of the plurality of die attach pads are separated by a photo-imageable mask. The plurality of die attach pads reduces the maximum stress created as a result of the mismatch of thermal expansion coefficients between the die and the die attach pads when compared to the stress created when employing a single, larger die attach pad.
According to another aspect of the present invention, a new process for fabricating a leadless plastic chip carrier is provided. The process has the steps of: depositing a photo-imageable mask on a first surface of a leadframe strip; imaging and developing the mask to define a plurality of die attach pads, at least one row of contact pads and a power/ground ring intermediate the die attach pads and the contact pads; depositing a plurality of layers on portions of the first surface exposed by the imaging and the developing for creating the at least one row of contact pads, the power/ground ring and the plurality of die attach pads; mounting the semi-conductor die to the die attach pads on a top surface thereof; wire bonding the semiconductor die to the contact pads; encapsulating the mask, the layers, and the die between a moulding compound and the first surface of the leadframe strip; etching back a bottom surface of the leadframe strip for exposing the contact pads and the die attach pads; and singulating the leadless plastic chip carrier from the leadframe strip.
According to yet another aspect of the present invention, a new process for fabricating a leadless plastic chip carrier is provided. The process having the steps of: applying a layer of photo-resist on a first surface of a leadframe strip; exposing and developing the layer of photo-resist to define a plurality of die attach pads, at least one row of contact pads and a power/ground ring intermediate the die attach pads and the contact pads between a remainder of the photo-resist; depositing a plurality of layers on portions of the first surface exposed by the exposing and the developing for creating the at least one row of contact pads, the power/ground ring and the plurality of die attach pads; stripping the remainder of the photo-resist; depositing a photo-imageable mask on the first surface and the plurality of die attach pads; imaging and developing the mask to expose a top surface of the plurality of die attach pads; mounting the semi-conductor die to the die attach pads on the top surface; wire bonding the semiconductor die to the contact pads; encapsulating the mask, the layers, and the die between a moulding compound and the first surface of the leadframe strip; etching back a bottom surface of the leadframe strip for exposing the contact pads and the die attach pads; and singulating the leadless plastic chip carrier from the leadframe strip
It is an advantage of an aspect of the present invention to mitigate internal stress between the die and the die attach pad resulting from differences in the coefficient of thermal expansion.
It is a further advantage of an aspect of the present invention to simplify printed circuit board assembly mounting. Providing an array of die attach pads rather than a single large die attach pad reduces lifting of the integrated circuit package caused by surface tension of the solder. Also, edge surface tension aids in self-alignment of the integrated circuit package on assembly with the printed circuit board. The force caused by edge surface tension is greater with an array of smaller pads rather than a single large pad.